Application-Specific Integrated Circuit (ASIC)
An ASIC is an integrated circuit designed and manufactured for one specific application rather than general-purpose use. Whereas a CPU runs arbitrary software and an FPGA reconfigures arbitrary digital logic, an ASIC’s silicon is physically committed to one function — and that constraint is exactly why ASICs deliver the highest performance, lowest power, and lowest per-unit cost achievable in semiconductor manufacturing. The trade-off is non-recurring engineering (NRE) cost in the millions of euros and a 12–24 month development cycle from RTL freeze to first silicon.
Key Facts
| Aspect | Detail |
|---|---|
| Definition | Integrated circuit designed for a single application (vs. general-purpose CPU/GPU) |
| NRE cost | €500K (mature 28nm node) to €100M+ (advanced 3nm with EUV masks) |
| Time to first silicon | 12–24 months typical (RTL → tape-out → fab → packaging → test) |
| Unit cost at 1M volume | €0.50 – €50 (vs. FPGA €15 – €200 for equivalent logic) |
| Power efficiency | 5–10× better than FPGA, 50–100× better than CPU for same workload |
| Clock frequency | 1–5 GHz achievable on advanced nodes (FPGAs cap around 1 GHz) |
| Process nodes (2026) | Mature: 180/130/65nm. Modern: 28/22nm. Advanced: 7/5/3nm EUV |
| Modification after tape-out | Impossible — any change requires new mask set (€500K+) |
Types of ASIC
Not all ASICs are equally custom. The industry distinguishes four tiers by how much silicon is custom vs. pre-designed:
- Full-custom ASIC — Every transistor placed by hand. Maximum performance, used in CPU cores and analog mixed-signal designs. NRE: €5M – €100M+.
- Standard-cell ASIC (semi-custom) — Designer composes the chip from a library of pre-characterized logic cells (NAND, flip-flop, etc.) provided by the foundry. The dominant model for digital ASICs in 2026. NRE: €500K – €10M.
- Structured ASIC / Gate Array — Most layers are pre-defined; the designer customizes only the top metal interconnect layers. Faster turnaround (
6 months), lower NRE (€200K), but lower performance than full standard-cell. Examples: eASIC (now Intel), Triad Semiconductor. - Hardened FPGA (FPGA-to-ASIC conversion) — A validated FPGA design ported to fixed silicon. Useful when FPGA design is proven but volume now justifies ASIC cost. Inovasense’s FPGA vs ASIC guide covers this conversion path.
ASIC vs FPGA Comparison
| Criterion | ASIC | FPGA |
|---|---|---|
| Performance | Highest (1–5 GHz) | High (200–800 MHz typical) |
| Power efficiency | Best in class | 2–10× higher than ASIC |
| NRE cost | €500K – €10M+ | €10K – €150K |
| Unit cost at 10K volume | €2 – €50 | €15 – €200 |
| Unit cost at 1M volume | €0.50 – €10 | Still €15 – €200 (no scaling) |
| Time to market | 12–24 months | 3–6 months |
| Reconfigurability after deployment | None — fixed silicon | Full — reprogram via OTA |
| IP protection | Excellent (mask-level obfuscation) | Moderate (bitstream is copyable) |
| Best for | High-volume, fixed-function, low-power, fast | Low-medium volume, evolving requirements, parallel processing |
The crossover point where ASIC becomes economical is typically 50,000 to 500,000 units, depending on complexity. Below that, FPGA wins on total cost.
Real-World ASIC Examples
ASICs dominate in markets where production volumes are high enough to amortize the NRE:
- Smartphone SoCs (Apple A-series, Qualcomm Snapdragon, MediaTek Dimensity) — Hundreds of millions of units; full-custom on 3–5nm nodes
- Cryptocurrency mining — Bitcoin SHA-256 ASICs like Bitmain Antminer; 100,000+ unit production runs at €1,500 – €5,000 per chip
- Network switching silicon — Broadcom Tomahawk, Marvell Teralynx; 12.8 – 51.2 Tbps switching in custom 5nm silicon
- AI accelerators — Google TPU, NVIDIA Tensor Cores (within GPU), Tesla Dojo, Cerebras WSE-3
- Consumer electronics — Smart TV main SoCs, gaming consoles (Sony PlayStation, Microsoft Xbox custom AMD silicon)
- Automotive — NXP S32, Renesas R-Car, Mobileye EyeQ ADAS chips
- IoT modules — Espressif ESP32, Nordic nRF, Bluetooth/Wi-Fi combo SoCs
When to Choose ASIC
Choose ASIC when production volume justifies the NRE and one or more applies: per-unit cost is a primary product constraint (consumer electronics, IoT at scale), power budget is extreme (battery devices, edge AI), GHz-class clock frequencies are required, IP protection is critical (proprietary algorithms in silicon), or product lifecycle is long with stable specifications.
Avoid ASIC when requirements may change post-design (any modification requires a new €500K+ mask set), volume is below ~50,000 units (FPGA total cost wins), or you cannot commit to the 12–24 month development timeline and verification rigor that ASIC tape-out demands.
The FPGA-First Strategy
For products with potential ASIC future, sophisticated teams use a two-phase approach: prototype and ship initial production on FPGA (3–6 months, low NRE), validate the design in the real market, then convert to ASIC once volume justifies the investment. This eliminates the biggest ASIC risk — designing the wrong thing and losing €2M+ on an unusable mask set. See our FPGA vs ASIC engineering guide for the decision framework.
Related Terms
- FPGA — Reconfigurable alternative to ASIC for low-medium volume
- SoC — System-on-Chip; modern SoCs are ASICs integrating CPU, memory, peripherals, and accelerators
- RTL Design — The hardware description methodology that produces both FPGA bitstreams and ASIC mask sets
- VHDL — Standard HDL for European ASIC and FPGA design
- DO-254 — Design assurance standard applicable to ASICs in airborne electronics
Inovasense ASIC Capabilities
While most projects benefit from our FPGA design services at low-to-medium volumes, Inovasense supports FPGA-to-ASIC conversion for clients whose validated FPGA designs have reached volumes justifying ASIC economics. We provide front-end RTL refinement, verification expansion, design-for-test (DFT) insertion, and partner with European foundry-services providers for back-end tape-out. For defense and aerospace projects requiring DO-254 design assurance or EU dual-use export compliance, our process includes the documentation packages needed for both ASIC and FPGA implementations.
Official References
- IEC 62368-1 — Safety requirements for electronic equipment — IEC, applicable safety standard for ASIC-containing consumer and industrial products
- JEDEC standards — Technical specifications for semiconductor packaging and ASIC interfaces (DDR memory, eMMC, etc.)
- DO-254 — RTCA design assurance standard for ASICs in airborne electronics