RISC-V — Open-Standard Processor Architecture
RISC-V (pronounced “risk-five”) is an open-standard instruction set architecture (ISA) based on reduced instruction set computing (RISC) principles. Unlike proprietary ISAs like ARM and x86, RISC-V is freely available under an open-source license — meaning anyone can design, manufacture, and sell RISC-V processors without paying royalties.
Why RISC-V Matters
| Aspect | RISC-V | ARM | x86 |
|---|---|---|---|
| License | Open, royalty-free | Licensed (per-core or per-unit royalties) | Proprietary (Intel/AMD only) |
| Customization | Full — add custom instructions | Limited — ARM templates only | None |
| Governance | RISC-V International (Swiss foundation) | ARM Holdings (SoftBank) | Intel Corporation |
| Sovereignty | No vendor lock-in | UK-based licensing | US-based |
| Cost to adopt | Zero licensing fees | $1M+ for architecture license | Not available |
RISC-V is the only major ISA where no single country or corporation controls the specification — making it the strategic choice for European semiconductor sovereignty.
RISC-V Architecture Overview
Modular Design
RISC-V uses a modular ISA — a small base instruction set with optional standard extensions:
| Extension | Name | Purpose |
|---|---|---|
| RV32I / RV64I | Base Integer | Core integer operations (32-bit or 64-bit) |
| M | Multiply/Divide | Hardware multiplication and division |
| A | Atomic | Atomic memory operations (multi-core synchronization) |
| F / D | Floating-Point | Single/double precision floating-point |
| C | Compressed | 16-bit instructions for code density (IoT) |
| V | Vector | SIMD/vector processing (AI, DSP) |
| B | Bit-manipulation | Cryptography, compression acceleration |
| H | Hypervisor | Hardware virtualization support |
The most common profile for embedded systems is RV32IMAC (32-bit with multiply, atomic, and compressed instructions).
RISC-V vs. ARM — Detailed Comparison
| Factor | RISC-V | ARM Cortex |
|---|---|---|
| Licensing model | Free, open standard | Per-unit or per-core royalty |
| Custom extensions | Full freedom to add custom instructions | Limited to pre-defined configurations |
| Ecosystem maturity | Growing rapidly (GCC, LLVM, Linux mainline) | Mature (20+ years) |
| Security extensions | Custom TrustZone-like implementations | ARM TrustZone (standardized) |
| AI/ML extensions | RISC-V Vector (RVV), custom accelerators | ARM Ethos, Helium, SVE2 |
| European support | EPI, OpenHW Group, CHIPS-JU funding | Used widely but not sovereign |
RISC-V in Europe — Semiconductor Sovereignty
The European Union has identified RISC-V as a strategic technology for reducing dependency on non-EU semiconductor IP:
- European Processor Initiative (EPI) — Developing RISC-V-based processors for HPC and automotive.
- CHIPS Joint Undertaking (CHIPS-JU) — EU funding for RISC-V pilot lines and design centers.
- OpenHW Group — European-led consortium developing verified, industrial-grade RISC-V cores (CORE-V family).
- Barcelona Supercomputing Center — RISC-V based European HPC accelerators.
RISC-V on FPGA
RISC-V cores are frequently implemented on FPGAs for:
- Prototyping custom SoCs — Validate processor extensions before ASIC tape-out.
- Soft-core processors — Deploy configurable RISC-V cores in FPGA-based products.
- Hardware security — Custom security extensions without third-party IP trust issues.
- Education and research — Open cores like PicoRV32, VexRiscv, CVA6 (Ariane).
| Core | Language | Pipeline | Target |
|---|---|---|---|
| PicoRV32 | Verilog | Single-issue | Tiny FPGA (iCE40) |
| VexRiscv | SpinalHDL | Configurable | Flexible embedded |
| CVA6 (Ariane) | SystemVerilog | 6-stage, 64-bit | Linux-capable SoC |
| BOOM | Chisel | Superscalar OoO | High-performance research |